The latest research by AnandTech shed new light on why AMD processors may have a problem with increasing the number of cores at the moment. Everything apparently crashes on the bus used.
A bus is a physical and digital connection between specific internal components of (in this case) a processor. In the AMD Ryzen 5000 based on the Zen 3 architecture, there are CCD (Compute Complex Die), i.e. a special type of computing matrices. It is in them that the eight processor cores are connected with, among others 32 MB shared level 3 cache and IFOP using Bi-Directional Ring Bus.
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This makes each element connected in a kind of circle in which information circulates in both directions at the same time. This does not sound bad, but in reality communication between the two most distant elements requires going through the “half of the other” elements. This, in turn, leads to an increase in latency and that is why Intel, among others, abandoned this bus 11 years ago in favor of a mesh topology.
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The mesh topology is a more advanced ring bus, but with additional direct connectivity points between components. AMD, in turn, passed a small rendez-vois with its even more advanced variation, because it consists in direct connection of all elements with each other with Ryzen Zen 2 processors with 4-core CCX blocks. Finally, in the current generation of Ryzen, AMD has opted for an 8-core CCX in the form of a CCD with an internal two-way ring bus.
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Coming to conclusions, it now looks like AMD may have to ditch the ring bus in the future in order to be able to increase the number of processor cores per CCD block.
