Intel, a brand new 6-core CPU shows a renewed cache design

An unprecedented 6-core CPU from Intel appeared in the SiSoftware Sandra database. This new processor may seem like a normal 6-core CPU, but the completely renewed cache design compared to that present in all current CPUs could indicate a CPU of new generation Core or Xeon.

Specifically, the processor has 6 cores and 12 threads, similar to other CPUs already on the market such as the Core i7-8700K and several Xeon models. To date in the ninth generation Intel Core family “Coffee Lake Refresh” there is no 6-core CPU equipped with Hyper-Threading, but the tenth generation “Comet Lake” it should have several proposals in the catalog with these characteristics.

The base frequency of 3 GHz for the cores and 2.2 GHz for the IMC leaves no room for assumptions, being a standard frequency for the “engineering sample ”, the test versions of the new CPUs that are tested during the various engineering stages of a new architecture.

Nonetheless, it is interesting to note that the platform on which this CPU was tested is supposedly a Supermicro dual socket system. The specific platform on which the test was carried out is the SuperMicro X12DAi-N SMC X12.

We have no details to identify the characteristics of this motherboard, besides the fact that it is clearly indicated as “Dual Socket“But strangely enough the SiSoftware database detects this processor as part of the Core series, while the Xeon series, generally known for dual socket support, are obviously shown as Xeon. This could be due to the nature of this chip: being an engineering sample, it can be mistakenly recognized by the software.

As already written, the cache project has been renewed for this new model, which has 9MB of L3 cache and, surprisingly, 1.25MB of L2 cache per core, which brings the total L2 cache to 7.5MB. For comparison, the 9th generation Intel Core CPUs have 256KB of L2 cache per core, the Core X series has 1MB of L2 cache per core, and the 10nm Ice Lake CPUs have 512KB of L2 cache per core.

The only architecture with a comparable L2 cache size – according to previous rumors – is the future “Tiger Lake“, Equipped with 1.25 MB of L2 cache per core. Tiger Lake solutions are expected in the mobile sector during 2020, based on a 10 nm ++ process and also equipped with an L3 cache updated to MB compared to the 2 MB of the current Core CPUs and to the 1,375 MB of the Core X CPUs.

There is however a problem: the L3 cache of the engineering sample appeared in the SiSoftware Sandra database does not correspond to the Tiger Lake architecture since 3 MB per core would mean 18 MB of L3 cache, while we know that this CPU has 9 MB of L3 cache (1.5 MB per core), even lower than the current 14 nm products.

There is a possibility that this 6 core chip could be a first attempt to “translate” an architecture designed for 10nm to 14nm, to face possible production problems. Intel, as already stated in the past and confirmed by the roadmap on production processes until 2029, has decided to cut the umbilical cord that has so far indissolubly linked the different architectures to specific production processes, so that you can have more freedom of maneuver.

The reduction of the L3 cache, in fact, would lead to a saving of surface and complexity which could partially compensate for the less efficient production process. Otherwise, it could be the first look at the unpublished Xeon CPU of the Ice Lake family at 10nm + which are expected to be presented over the next year.