AMD, Intel, ARM, Samsung, Qualcomm and TSMC have come together to form a common and open standard for Chiplets. A much smaller version of processors, chipsets have seen tremendous growth in design, development, and adoption in the semiconductor space in recent years. Universal Chiplet Interconnect Express (UCIe), aims to standardize die-to-die interconnects for chipset projects with an open source approach.
Leading manufacturers and major chip makers have come together to announce that they are forming a new open standard for chip interconnects. UCIe hopes to simplify and standardize array-to-array connections in hardware and software. Eventually, this approach could help chip, CPU, chipset, and SoC designers and manufacturers easily and efficiently mix and match chipsets from different companies and create custom solutions.
Chiplets are essentially small blocks of integrated circuits. They are smaller than a traditional monolithic CPU and generally perform fewer tasks. Chiplets generally take the load off the central processing cores. Interestingly, the CPUs themselves can be designed as chipsets. In fact, Intel, ARM, and AMD are currently leading the development of processors that contain multiple chipsets. These new generations of CPUs have some performance cores and some efficiency cores. Other chiplets that are part of the package include the integrated GPU, NPU, and often times RAM and internal storage.
The UCIe has already ratified a UCIe 1.0 specification. This first stage covers the physical layer of array-to-array I/O, array-to-array protocols, and software that leverages the PCI Express and Compute Express Link standards. The group still needs to finalize the form factor and other finer details.
As tech giants build more and more proprietary hardware, an affordable, open source chiplet design architecture can help significantly reduce the time required for hardware and software design, development, and testing. However, it’s unclear when chip designers and electronics manufacturers will have access to chips built using the new open source standard.
Source: UCIe
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