AMD will significantly improve the fourth-generation EPYC memory subsystem

Phoronix’s search for Error Detection and Correction (EDAC) codes for the next generation of EPYC processors, which AMD revealed, provided us with a lot of information about them. Today we learned that even the 4th generation EPYC memory subsystem will be improved accordingly.

The fourth generation EPYC memory subsystem will be one of a kind. AMD will take care of that

It turns out that AMD EPYC, codenamed Genoa, will support unprecedented bandwidth and memory capacity “per socket”. It is certain that they will be compatible with the DDR5 standard in the form of RDIMM and LRDIMM modules, and in addition they will support up to 12 memory controllers per socket, which is four more compared to the current EPYC processors. However, it is still unknown how many DIMMs per channel they will support.

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Theorized, the alleged twelve 64-bit DDR5 memory channels would increase the throughput at the CPU-DRAM level of Genoa processors from 204.8 to 460.8 GB / s per socket compared to current AMD server processors supporting DDR4-3200. However, the memory bandwidth alone will not be the only improvement, because the twelve memory channels will also allow you to increase the overall memory capacity from 4 to even 6 TB, thanks to, among others, 512GB of DDR5 modules from Samsung.

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The case will be further improved if 4th generation EPYC processors will support two modules per channel, because then this capacity will increase to 12 TB and higher thanks to LRDIMM, but at the expense of performance.