Compute Express Link can be the cornerstone for pairing Intel Xe graphics cards

During Intel’s data center conference Inteconnect Day 2019, CXL, a new interface for communication between circuits, was presented. Unlike PCI Express, which is a pure interface for communication, CXL is both a link layer and an integrated control unit for communication between processors. Information about the standard suggests that it may link Intel’s upcoming graphics cards in the Xe family.

CXL is an abbreviation of Compute Express Link, an open standard that in addition to Intel is also backed by Alibaba, Cisco, Dell EMC, Facebook, Google, HPE, Huawei and Microsoft. The standard is based on the physical and electrical link storage in PCI Express for fast communication between circuits.

Initial implementations of CXL are based on PCI Express 5.0 for physical and electrical connections between processors and other circuits, with graphics cards and programmable circuits (FPGAs) as likely first applications. The difference between CXL and PCI Express is that the former supports memory synchronization between connected devices.

CXL consists of three different protocols. Secondly, CXL.io, which replaces PCI Express, and is responsible for the detection and configuration of devices. The other two protocols are called CXL.cache and CXL.memory, and it is these that form the basis for the synchronization of cache memory between connected devices that represent the potential for paired graphics cards.

Precisely synchronization of cache between devices suggests that CXL can become a key component in pairing graphics cards, so-called multi-GPUs, for Intel’s upcoming graphics cards in the Intel Xe family. Previous multi-GPU solutions have relied on PCI Express connections, which lack the ability to synchronize memory information between connected devices.

AMD’s and Nvidia’s solutions for multi-GPUs have been based on physical hardware links, SLI in Nvidia’s case and Crossfire in AMD’s case, and software – based solutions where the rendering of images is distributed between the paired graphics cards. These solutions have been drawn with considerable latency in communication and also limited utilization of the graphics card’s capacity in game titles that are not optimized for multi-GPUs.

Current implementations of paired graphics cards over PCI Express suffer from limitations in that the resources of paired graphics cards are isolated from each other. The memory pool of a graphics card is isolated from other graphics cards, and the communication between the various paired devices introduces latency that leads to limited utilization of the graphics card’s resources.

The synchronization of CXL links means that a unified memory pool can be created for connected devices, which should make it possible to scale performance without many of the performance losses that traditional multi-GPUs suffer from. If CXL is used in Intel’s upcoming graphics card family Xe, it could mean an advantage over AMD and Nvidia, which have toned down the focus on multi-GPUs in recent years.

When the standard started with Intel, it is likely that the first implementation will take place in Intel’s graphics card families, but since it is an open standard, it is free for competitors to also build solutions for multi-GPUs around CXL. As CXL 1.0 is based on PCI Express 5.0, such solutions are not to be expected until next year at the earliest, and work on CXL 2.0 is already underway.

The graphics card family Intel Xe is expected to be launched in 2020. Whether the graphics cards will use CXL for pairing remains to be seen.

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