AMD GPU, the future is modular: patented an active bridge with integrated cache

AMD continue to work for bring the concept of chiplets and modularity also in the world of GPUs. The abandonment of monolithic designs has proven successful with the Ryzen 3000 and 5000 desktop processors, giving the company speed and flexibility in design, better production yields and superior control over performance and power consumption.

A few months ago a patent had made clear AMD’s intentions and, in these days, a second intellectual property expands the concept by proposing the use of an active bridge, even with a cache, rather than the use of a passive bridge.

A passive bridge has the task of being vigilant, that is to pass and manage the connections and communications between the various chiplets equipped with computing resources, while an active bridge performs multiple tasks and, in addition to that of “vigilant”, in this case it also operates last level cache, a memory available to all chiplets. This design allows to ensure interconnection with a high bandwidth at low latency between the various chiplets, thus preventing each chiplet from having a dedicated cache.

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In some ways, this patent – which, like any intellectual property, is not necessarily applied – seems to displace what we currently call Infinity Cache (big news of the RDNA 2 architecture) in the bridge. A project of this type also has the advantage of expose logs and caches as a single block, making life easier for developers.

It is unclear whether this modular design will already find application with future architecture-based solutions RDNA 3 or later: AMD has not yet exposed itself on the matter, although recently rumors have circulated about the arrival of an accelerator dedicated to the HPC world based on CDNA 2 architecture and a MCM (multi-chip module) project.

In this specific case, the patent seems to indicate more the design of an APU than a real GPU, but a similar implementation could also affect dedicated GPUs for the various market sectors with due differences.