The road taken by AMD with Ryzen 3000, Threadripper 3000 and EPYC Rome processors could also be beaten by Intel to speed up the release of new processors and advance more easily on the production process front and save money.
During the USB Global TMT financial conference, Intel's Chief Engineering Officer, Murthy Reduchintala, explained to investors and analysts that 50% of the research and development budget for processors is spent on updating complementary components to the cores at the last production process. A modus operandi that apparently is no longer sustainable.
The future painted by Reduchintala recalls what AMD implemented with Zen 2 architecture: in Ryzen 3000 desktop processors the cores are made at 7 nanometers, while the chip responsible for the input and output operations (memory controller, connectivity and more) is produced at 12 nanometers.
In fact, not all components of a processor respond well to miniaturization (because of different signals, interferences, etc.) and do not get the same benefits that the computing cores have instead.
“We end up spending about 50% of research and development in porting a technology that does not return the same benefit that can be achieved by scaling the cores. Decoupling them and realizing them with a different cadence allows to accelerate the product roadmap“.
As you can see in the slide below, Intel is not new to this concept, it already talked about it in 2017. The problem is that AMD applied this type of design before the Santa Clara house. Intel relies on solutions with different units on the same chip, interconnected at high speed for connect (for example) 22 nanometer chips to 10 and 14 nanometer solutions, all forming a single processor, but also something different.
At the moment Intel continues to offer “monolithic” CPUs formed by components made with a single production process, which would not be a problem if it were not for the delay of 10 nanometers, slipped by several years.
The breakthrough in terms of Intel CPU design is likely to take place starting from 2021/2022 with 7 nanometers, with a wider use of 3D packaging technologies such as Foveros, EMIB and other solutions for the realization of hybrid chips, not only with different cores and components, but also different processes.